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Verilog Analyzer user guide

Verilog Analyzer lets you synthesize Verilog / SystemVerilog in the browser (no install) and inspect synthesis stats, FSM state diagrams, gate-level schematics, and Yosys JSON netlists. The engine is Yosys WebAssembly via @yowasp/yosys.

👉 Open the tool: Open Verilog Analyzer

What you can do​

  • Edit multiple .v / .sv files in tabbed editors (syntax highlight, font, line count, theme)
  • Pick one Top module and Include only the files that participate in synthesis
  • Run Synthesis once to get logs & stats and a first FSM extraction (from the log flow, default Top)
  • Use the instance hierarchy tree together on Synthesis / FSM / Schematic tabs (selection, expand/collapse, Total cells column)
  • On FSM Diagram, view FSM as Mermaid (re-extracts when this tab is active and you change the selected module)
  • On Circuit Schematic, press “Generate schematic” only there to build netlistsvg + ELK wiring (heavy work stays in this tab)
  • Download Netlist JSON after synthesis
  • Load Example or Extract workspace as ZIP

Great for checking synthesis pass / fail and FSM shape before courses or reviews.
(Not a replacement for) vendor FPGA flows, timing sign-off, or P&R.

Layout (overview)​

AreaRole
File tabsSwitch open files, rename, close, new file / upload
Code editorSyntax highlight, font / line count / light·dark theme
File managerTop radio, Include checkboxes, ZIP extract, Example
ToolbarWASM status, ? help, Run Synthesis, result tab switch
ResultsSynthesis Result / FSM Diagram / Circuit Schematic

Toolbar · WASM · Run Synthesis​

  • Lightning (circle)
    • Green: YoWASP WASM ready
    • Red: load failed — use retry
    • Gray + spinner: loading
    • Tooltip shows state (no text label on the button).
  • ?: short popup (WASM size, cache, etc.)
  • Run Synthesis: synth -top <Top>, log parsing, netlist cache, then one FSM pass from the post-synthesis log (default Top).
    Schematic (netlistsvg) is not drawn by this button alone.

The three result tabs switch on the same row to the right.

Tabs​

Synthesis Result​

  • Collapsible Raw Synthesis Log
  • With a netlist: instance hierarchy + design hierarchy stats and stat summary for the selected instance

What “Cells” means in the table​

  • Total cells matches Yosys stat Number of cells for that scope (instances inside that module/hierarchy slice).
  • Rows like $_AND_, $_DFF_* (names starting with $_) are primitive cell counts by kind.
  • Picking a higher module often shows only Total cells (submodules as blocks) with no $_ rows; drill into instances in the tree to see primitives.
  • The pie chart is usually based on those primitive rows, so it can differ from Total cells when only hierarchical instances are present.

FSM Diagram​

  • Meaningful after synthesis completes.
  • When this tab is active, changing the selected instance (RTL module) triggers a YoWASP re-run to re-extract FSM (other tabs do not auto re-run, to save load).
  • Choosing Top applies a pass that strips child instances before proc so lower-module FSMs do not mix in.
  • Diagram is Mermaid.

Circuit Schematic​

  • Gate-level drawing via netlistsvg + ELK.
  • No auto generate. Press “⚡ Generate schematic” in the panel to start.
    Large designs may take tens of seconds; errors / huge netlists may fall back to a summary (mock) SVG.
  • Changing instance path or re-synthesizing clears the old SVG — generate again.
  • Pan / zoom: drag, wheel (wheel hooks to the canvas only when this tab is active).
  • Names: internal Yosys keys like $paramod$hash\module are shortened for display where possible.
  • Click SVG blocks to drill down when supported; tree / breadcrumb share the same instance path.

Instance hierarchy (all three tabs)​

After synthesis, Synthesis / FSM / Schematic share one tree.

  • Selected row (Top or instance/child/…) persists across tab switches.
  • Expand/collapse state is shared.
  • Total cells column uses the same synthesis stat basis.

Schematic drawing uses this path only after you press generate.

Quick start​

1. Try the example​

  1. Open Verilog Analyzer.
  2. Load the default Example from the file manager.
  3. Top is the synthesis root.

2. Bring your code​

  • Upload or new file
  • include: when multiple files, only checked files join synthesis
  • Exactly one Top

3. Run Synthesis​

  • Run Run Synthesis → logs appear under Synthesis Result.
  • First visit / cold cache may download WASM (can take a while).
  • On success: hierarchy, stats, Netlist JSON download.

4. FSM​

  1. Open FSM Diagram.
  2. Pick a module in the tree (or keep selection) — FSM extracts for that RTL context.

5. Schematic​

  1. Open Circuit Schematic.
  2. Align instance path in the tree, then “⚡ Generate schematic”.
  3. Pan/zoom; use ↻ regenerate if needed.

6. ZIP​

  • Extract (ZIP) downloads the current workspace files.

File manager terms​

TermMeaning
TopSynthesis top module (one radio)
IncludeWhether this file is in the current synthesis set
ClosedTab closed only; Top/Include in the manager may persist

Editor · theme​

  • Font size, visible lines, light/dark from the editor toolbar.
  • Some keys may be shared with Waveform Editor (theme storage).

Browser · performance​

  • WASM synthesis, FSM re-run, and (when used) ELK use CPU & RAM. Large designs can be slower or fail vs desktop Yosys.
  • Schematic runs only when you open the tab and press generate, so the UI stays lighter while you only browse instances.
  • Prefer recent Chrome / Edge / Firefox.

With Waveform Editor​

  • Verilog Analyzer for RTL synthesis, FSM, schematic overview.
  • Waveform Editor for bus / protocol timing diagrams and documentation.