Active designer at a Global Top 5 Fabless company, planning and delivering practical RTL/ASIC/FPGA courses.
FREE TOOLS
Browser-Based Design Tools — No Installation Required
Synthesize and simulate Verilog, view waveforms, and draw timing diagrams — all in your browser.
Everything here is free, and we keep adding more tools over time.
You'll want these again — bookmark this page so you can jump back in one click.
▶️
Verilog Simulator
No install—run RTL simulation free in your browser, fast, and view waveforms right away.
🔬
Verilog Analyzer
No install—analyze Verilog free and fast in your browser and see behavior and structure at a glance.
📈
Waveform Editor
No install—sketch timing waveforms and diagrams free and fast, then export to an image when you need it.
🔢
HEX·DEC·OCT·BIN calculator
No install—convert and crunch number bases in one place, free and fast in your browser.
MINI GAMES (XP UP)
Play a little each day—your rank becomes XP
Sign in: daily visits stack XP, and consecutive days add a small bonus.
Baseball, guess, slide, and ring roulette start a new round every midnight KST; when it closes, your rank becomes XP.
COMMUNITY & CHANNELS
Questions on Discord — videos on YouTube
Ask when you are stuck; stay updated together.
Connect with the SGDH crew in real time on Discord and on video via YouTube.
Inflearn & Fast Campus course discounts are also on the Member Benefits page.
ROADMAP
From beginner to pro —
a leveled course roadmap
Click a card to go straight to the course page.
Inflearn and Fast Campus each host different curricula so nothing overlaps — they connect as one path.
Category / Level
L1. Beginner (Freshman–Sophomore)
L2. Job-Ready (Junior–Senior)
L3. Grad / Junior Engineer
L4. Working Professional (Advanced)
Language (Essential)
사전지식 !! (C 언어, 논리회로)
BasicTheory
We strongly recommend completing these prerequisites before starting hardware design studies.
설계독학맛비의 Verilog HDL Season0 (문법 마스터 클래스)
OpenBasicHands-onTheoryS125y
Essential Verilog HDL syntax fundamentals for absolute beginners.
System Verilog LRM 문법 강의
Planned 26yBasicHands-onTheory26y
Explains the SystemVerilog grammar system in a structured, industry-ready way.
Verilog HDL Season2 (AMBA AXI4 인터페이스)
OpenAdvancedHands-onTheoryS226y
Covers AMBA AXI4 interface design at the project level.
설계독학's Verification Guide Assertion / Coverage / UVM (27y)
Coming soonAdvancedHands-onTheory27y
Covers how to boost verification productivity with Assertion/Coverage/UVM flows.
FPGA / Embedded
설계독학맛비's FPGA Season2
Planned 26yAdvancedHands-onTheory26y
Advanced FPGA course covering system-level design and verification.
Career & Practice
Verilog 면접 기출 문제 풀이 (Season1)
OpenBasicHands-onTheoryS126y
Intensively covers recurring RTL/timing interview questions for job seekers.
RISC-V로 배우는 컴퓨터 구조
Coming soonBasicHands-onTheory27y
Re-examines computer architecture from a design perspective using RISC-V.
AI HW 설계 바이블
OpenAdvancedHands-onTheory26y
Organizes AI computation architecture and HW implementation strategy from a design perspective.
RISC-V 실전 설계
Coming soonAdvancedHands-onTheory28y
Covers RISC-V core design/verification from a practical SoC perspective.
실시간 영상처리
Coming soonAdvancedHands-onTheory27y
Covers decomposing and optimizing image processing pipelines into hardware architectures.
Verilog 면접 기출 문제 풀이 (Season2)
Planned 26yAdvancedHands-onTheoryS226y
Extends to advanced interview problems for experienced/senior engineers in Season 2.
High Level Synthesis (26y)
Planned 26yAdvancedHands-onTheory26y
Covers HLS adoption strategy and RTL collaboration points aligned with real development workflows.
INSTRUCTORS
Meet Our Instructors
Learn practical skills systematically with industry experts across domains.
PhD in SoC design, covering all areas of design and development to co-create a practice-focused curriculum.
DD
Full-Stack Engineer
From a foreign-affiliated SW background, handles ARM embedded SW/HW integration and creates practical Linux/FPGA system courses.
이파란
System SW Engineer
Senior-level digital design engineer creating practical coding-test and interview-focused Verilog courses.
에타
RTL Engineer
Specializes in HLS and design automation, preparing advanced design productivity improvement tracks.
크맨
HLS Master
Creates content translating processor research-based design/verification methodologies into practical applications.
세미푸스
Computer Science PhD
Provides learning paths focused on FPGA embedded systems used in defense industry, from an HW-SW integration perspective.
리어리
FPGA Embedded
Explores how embedding AI in RTL workflows pays off in real design work, and turns experiments into content that shows where it actually helps.
Nate
AI RTL Explore
We are recruiting crew members to share knowledge and grow together with the SGDH team.