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Verilog Simulator — SGDH
tb.v
workspace
›
tb.v
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// testbench top
`timescale
1ns
/
1ps
module
tb
;
logic
clk
;
logic
rst_n
;
dut
u_dut
(
.*
)
;
initial
clk
=
0
;
always
#
5
clk
=
~
clk
;
initial
begin
rst_n
=
0
;
repeat
(
2
)
@
(
posedge
clk
)
;
rst_n
=
1
;
@
(
posedge
clk
)
;
Terminal
Output
Problems
TERMINAL
— simulation and log output (coming soon).
Ln 1, Col 1
Spaces: 2
UTF-8
LF
Verilog
SGDH